三相電壓不平衡下DDSRF-PLL與DSOGI-PLL的鎖相誤差檢測與補(bǔ)償方法

祁永勝 李 凱 高暢毓 薛騰躍 游小杰

三相電壓不平衡下DDSRF-PLL與DSOGI-PLL的鎖相誤差檢測與補(bǔ)償方法

祁永勝1,2李 凱1高暢毓1薛騰躍1游小杰1

（1. 北京交通大學(xué)電氣工程學(xué)院 北京 100044 2. 國網(wǎng)山西省電力公司忻州供電公司 忻州 034000）

由于高滲透的分布式電源、多樣化的負(fù)荷類型以及電網(wǎng)故障等因素，并網(wǎng)點三相電壓不僅存在幅值不平衡，而且會出現(xiàn)相位不平衡現(xiàn)象。這種情況下，廣泛應(yīng)用的解耦雙同步坐標(biāo)系鎖相環(huán)（DDSRF-PLL）和雙二階廣義積分器鎖相環(huán)（DSOGI-PLL）無法獲得精確的同步信息。為此，該文在論證這兩種鎖相環(huán)具有理論等價性的基礎(chǔ)上，闡釋三相電壓不平衡與鎖相誤差的內(nèi)在關(guān)系，進(jìn)而提出一種鎖相誤差的補(bǔ)償方法，實現(xiàn)幅值和相位不平衡下的準(zhǔn)確鎖相。所提方法僅需對電壓采樣值進(jìn)行簡單計算即可獲得不平衡相位和鎖相誤差，實現(xiàn)開環(huán)相位補(bǔ)償，無需修改原有鎖相結(jié)構(gòu)，具有良好的拓展性。最后，通過仿真和實驗驗證了所提方法的有效性。

三相電壓不平衡 鎖相環(huán)（PLL） 不平衡相位檢測 鎖相誤差補(bǔ)償

0 引言

近年來，隨著電力電子技術(shù)的發(fā)展，涌現(xiàn)出大量的并網(wǎng)電氣設(shè)備，如分布式發(fā)電系統(tǒng)的接口變換器和各種電能質(zhì)量治理裝置，在增強(qiáng)供電可靠性的同時也改善了電能質(zhì)量[1-3]。這些并網(wǎng)變換器需要通過鎖相環(huán)來實時獲取并網(wǎng)點電壓的頻率和相位信息，以實現(xiàn)其與電網(wǎng)系統(tǒng)的協(xié)調(diào)控制[4-6]。然而，大量非線性負(fù)荷的接入、不均衡分配、線路阻抗差異、電網(wǎng)故障和采樣等[7]使得并網(wǎng)點電壓存在不同程度的諧波污染、三相不平衡以及直流偏置等情況，為此，文獻(xiàn)[8-10]對諸多學(xué)者提出的非理想電網(wǎng)電壓下的三相鎖相環(huán)方法進(jìn)行綜述、建模及設(shè)計。它們均以理想三相電壓下的單同步坐標(biāo)系鎖相環(huán)（Single Synchronous Reference Frame-Phase Locked Loop, SSRF-PLL）為基礎(chǔ)展開研究[11-12]。為拓展SSRF-PLL在三相電壓不平衡工況下的應(yīng)用，文獻(xiàn)[13-15]通過增加一個負(fù)序旋轉(zhuǎn)坐標(biāo)系，提出解耦雙同步坐標(biāo)系鎖相環(huán)（Decoupled Double SRF-PLL, DDSRF-PLL），但其僅能消除負(fù)序分量的影響。為改善其濾波性能，文獻(xiàn)[16-19]采用基于二階廣義積分器（Second Order Generalized Integrator, SOGI）的鎖相結(jié)構(gòu)，其中應(yīng)用最為廣泛的是雙二階廣義積分器鎖相環(huán)（Double SOGI-PLL, DSOGI-PLL）。為簡化SOGI結(jié)構(gòu)，文獻(xiàn)[20-22]提出了復(fù)系數(shù)濾波器，即降階廣義積分器[23]，它們本質(zhì)上均是應(yīng)用帶通濾波特性實現(xiàn)對基波正序分量的單位增益、零相移提取。對于并網(wǎng)點電壓存在較為嚴(yán)重的諧波污染情形，可將多個帶通濾波器疊加形成一系列梳狀濾波器來實現(xiàn)較好的濾波效果，如對電壓采樣信號進(jìn)行延遲[24]、嵌入重復(fù)內(nèi)模[25]、做滑動均值處理[26]和離散傅里葉分解[27-28]，或采用多種濾波方法[29-30]來消除諧波。

值得注意的是，由于負(fù)載差異或電網(wǎng)故障等[31]會導(dǎo)致三相電壓存在幅值和相位兩方面的不平衡[32]，而上述文獻(xiàn)并未考慮相位不平衡下的鎖相情形。文獻(xiàn)[33]采用延遲信號對消方法在實現(xiàn)濾波和幅值標(biāo)幺化的基礎(chǔ)上，利用不平衡相位對鎖相誤差進(jìn)行補(bǔ)償，雖具有較好的效果，但結(jié)構(gòu)復(fù)雜、計算繁瑣。文獻(xiàn)[34]利用自適應(yīng)Clarke變換以實現(xiàn)三相電壓幅值和相位不平衡下的精確鎖相，運用帶通濾波器實現(xiàn)濾波，并給出相位誤差校正算法，但同樣存在結(jié)構(gòu)復(fù)雜和計算負(fù)擔(dān)大的缺陷。而文獻(xiàn)[35-36]雖提出相對前述文獻(xiàn)較簡單的相位補(bǔ)償方法，但并未從本質(zhì)上分析相位不平衡與鎖相誤差的內(nèi)在關(guān)系。針對該問題，本文基于理論推導(dǎo)，以DDSRF-PLL和DSOGI-PLL為例，揭示不平衡相位和鎖相誤差的內(nèi)在關(guān)系，進(jìn)而提出一種簡易可行的不平衡相位檢測與鎖相誤差補(bǔ)償方法，該方法具有普適性，有著較高的補(bǔ)償精度和良好的拓展性。

1 DDSRF與DSOGI的理論等價性

圖1 解耦雙同步坐標(biāo)系鎖相環(huán)的結(jié)構(gòu)框圖

圖2 雙二階積分器鎖相環(huán)的結(jié)構(gòu)框圖

國標(biāo)將三相電壓不平衡闡述為幅值和相位兩方面的不平衡[32]。由于諧波和直流分量等可通過濾波器消除，這里僅考慮三相不平衡電壓為

式中，sa、sb、sc分別為A相、B相及C相電壓；sma、smb、smc分別為其對應(yīng)的幅值；g為電壓角頻率；Dqb、Dqc分別為以A相電壓相位為基準(zhǔn)的B相和C相的不平衡電壓相位。

將式（1）所示的包含幅值和相位不平衡的三相電壓作為DDSRF-PLL與DSOGI-PLL兩種方法的輸入信號，并以A相電壓定向，可得到式（1）的兩相靜止坐標(biāo)系表示為

式中，1～4為中間變量，是關(guān)于sma、smb、smc以及Dqb、Dqc的函數(shù)，其表達(dá)式如附錄式（A1）～式（A4）所示。

進(jìn)一步地，利用輔助角公式，可將式（2）整理為

其中

對于DDSRF-PLL，通過正、負(fù)同步旋轉(zhuǎn)坐標(biāo)系結(jié)合解耦網(wǎng)絡(luò)和低通濾波器實現(xiàn)諧波分量的濾除和基波正、負(fù)序分量的分離[13-15]?；赿軸電壓定向，可得到正、負(fù)同步旋轉(zhuǎn)坐標(biāo)變換后的信號，分別為

經(jīng)解耦網(wǎng)絡(luò)消去式（4）和式（5）的二倍頻分量后，可得

同理，在式（3）的基礎(chǔ)上，根據(jù)式（8）所示的兩相靜止坐標(biāo)系下的提取正序分量的對稱分量法表達(dá)式[19]，可得到基于DSOGI-QSG的兩相靜止坐標(biāo)系下的正序電壓分量如式（9）所示。

同樣地，可得到DSOGI-PLL的正序電壓分量在正序同步旋轉(zhuǎn)坐標(biāo)系下的表達(dá)式為

2 不平衡相位檢測與鎖相誤差補(bǔ)償方法

2.1 鎖相誤差的內(nèi)在機(jī)理分析

為獲得三相不平衡電壓下的鎖相誤差，根據(jù)鎖相的穩(wěn)態(tài)關(guān)系，將式（6）或式（10）的q軸分量調(diào)節(jié)至零。由于兩種鎖相環(huán)的表達(dá)形式一致，這里統(tǒng)一記為sq，令其為零并經(jīng)三角函數(shù)恒等變換，可得

進(jìn)一步地，由于三相鎖相環(huán)常對每相電壓進(jìn)行幅值標(biāo)幺化以消除幅值不平衡的影響[33]，從而保證鎖相環(huán)控制精度。為便于分析，這里將sma、smb、smc取為1，后續(xù)以上標(biāo)“*”表示幅值標(biāo)幺化。結(jié)合附錄中式（A1）～式（A4），可將式（13）簡化為

式（14）表明，Dqcorrect與Dqb、Dqc具有映射關(guān)系。

將Dqcorrect作為因變量，Dqb、Dqc作為自變量，經(jīng)反正切運算，可得式（15）所示的Dqcorrect與Dqb和Dqc的關(guān)系。由于反正切函數(shù)的值域為[-p/2,p/2]，且實際的相位不平衡程度有限，這里以Dqb、Dqc在[-p/6,p/6]內(nèi)的情形分析。

由式（15）可繪制出Dqcorrect=(Dqb,Dqc)的三維圖形，如圖3所示。為直觀顯示，圖3的坐標(biāo)單位以角度標(biāo)注。通過分析圖3的曲面關(guān)系，有如下結(jié)論：

圖3 Dqcorrect與Dqb、Dqc的三維關(guān)系曲面

（2）鎖相誤差曲面近似為平面，并與零平面相交于直線i：Dqb=Dqc，Dqorrect=0，如圖3中的點、點和點，表明Dqb和Dqc取值相等時，不會產(chǎn)生鎖相誤差。而且該曲面以直線i為界，當(dāng)處于直線i上方的A1區(qū)域時，Dqb＜Dqc，Dqcorrect＞0；而處于i下方的A2區(qū)域時，Dqb＞Dqc，Dqcorrect＜0。

（3）該曲面上關(guān)于直線i軸對稱的點，Dqcorrect的幅值相同，符號相反，如圖3中的點與點。

（4）處于曲面與直線i平行直線上的點，它們的Dqcorrect取值相等，如圖3中的點和點以及點和點。

2.2 鎖相誤差求解方法

圖4 Dqcorrect的平面近似方法

圖4所示的平面近似方法以點、、確定區(qū)域A1，以點、、確定區(qū)域A2，并由點、、確定區(qū)域A3。因此，可以很容易地得到區(qū)域A1、區(qū)域A2和區(qū)域A3的數(shù)學(xué)表達(dá)式分別為

2.3 不平衡相位檢測方法

圖5Dqb與Dqc檢測中的電壓采樣情形

Fig.5 Voltage sampling in the detection ofDqbandDqc

將式（1）進(jìn)行三角恒等變換為正弦形式，并考慮幅值標(biāo)幺化，可得三相電壓表達(dá)式為

3 仿真分析

3.1 不平衡相位與鎖相誤差內(nèi)在關(guān)系的仿真分析

為驗證理論分析的正確性，搭建Matlab仿真模型，并將不同Dqb和Dqc取值下的三相電壓和兩種鎖相方法的鎖相結(jié)果進(jìn)行仿真如圖6所示。

圖6 相位不平衡下DDSRF和DSOGI-PLL的仿真結(jié)果

Fig.6 Simulation results of DDSRF and DSOGI-PLL at unbalanced phase angles

表1 相位不平衡下兩種鎖相環(huán)的鎖相數(shù)據(jù)

Tab.1 Data of two PLLs at unbalanced phase angles （單位: °）

3.2 不平衡相位檢測與補(bǔ)償方法的仿真驗證

圖7 不平衡相位的檢測結(jié)果

Fig.7 Detection results of unbalanced phase angle

圖8 時，經(jīng)相位補(bǔ)償前后的DSOGI-PLL的鎖相結(jié)果

4 實驗驗證

4.1 不平衡相位與鎖相誤差內(nèi)在關(guān)系的實驗驗證

相位不平衡下DDSRF-PLL和DSOGI-PLL的實驗結(jié)果如圖9所示。圖9中的不平衡工況分別按照圖6的仿真工況設(shè)置，每個圖中的波形從上至下依次為并網(wǎng)點三相電壓波形（sa,sb,sc）、DDSRF- PLL估測相位的DA值（DDSRF_DA）以及DSOGI-PLL估測相位的DA值（DSOGI_DA）。其中，相位不平衡的三相電壓由Chroma 61705型三相可編程電壓源產(chǎn)生。圖9的實驗結(jié)果與圖6的仿真結(jié)果基本一致，僅在數(shù)值上有微小差異，表明DDSRF-PLL及DSOGI- PLL兩種鎖相方法在三相電壓相位不平衡下鎖相的等價性，同時驗證了鎖相誤差與不平衡相位內(nèi)在關(guān)系的理論分析。

4.2 不平衡相位檢測與補(bǔ)償方法的實驗驗證

進(jìn)一步地，選擇圖9h所示的鎖相誤差最大的情形，并以DSOGI-PLL為例，對本文提出的不平衡相位檢測和補(bǔ)償方法進(jìn)行實驗，相位補(bǔ)償前后的實驗結(jié)果如圖10所示。圖10中，各圖波形從上至下依次為并網(wǎng)點三相電壓波形（sa,sb,sc）和對應(yīng)估測相位的余弦值（cosa_DA, cosb_DA, cosc_DA），其中后者通過數(shù)模轉(zhuǎn)換（DA）讀出。圖10a和圖10b表明，補(bǔ)償后相較于補(bǔ)償前相位滯后1.425 ms，精確補(bǔ)償后相位滯后僅為75ms；而圖10c～圖10e則表明，基于一次、二次以及平面近似的方法補(bǔ)償后相位滯后分別減小為250ms、325ms和225ms。這說明精確補(bǔ)償具有最高的補(bǔ)償精度；而近似算法則以略低的補(bǔ)償精度為代價實現(xiàn)了簡化計算，選擇時需要對補(bǔ)償精度和計算量進(jìn)行折中。

圖9 相位不平衡下DDSRF和DSOGI-PLL的實驗結(jié)果

Fig.9 Experimental results of DDSRF and DSOGI-PLL at unbalanced phase angles

（a）相位未補(bǔ)償

（b）精確補(bǔ)償

（c）一次近似補(bǔ)償

（d）二次近似補(bǔ)償

（e）平面近似補(bǔ)償

圖10 相位補(bǔ)償前后的實驗結(jié)果

Fig.10 Experimental results before and after phase compensation

5 結(jié)論

本文以DDSRF-PLL和DSOGI-PLL這兩種常用于三相電壓幅值不平衡的鎖相方法為基礎(chǔ)，考慮幅值和相位兩方面的不平衡，論證了二者的鎖相等價性，并說明電壓相位不平衡會導(dǎo)致二者存在固有鎖相誤差。針對該問題，本文基于鎖相環(huán)的穩(wěn)態(tài)特性，在理論推導(dǎo)的基礎(chǔ)上，揭示了鎖相誤差和不平衡相位的內(nèi)在關(guān)系，進(jìn)而提出鎖相誤差的求解方法和不平衡相位的檢測方法，并通過仿真和實驗驗證了所提方法的準(zhǔn)確性。本文揭示的鎖相誤差和不平衡相位的內(nèi)在關(guān)系為三相電壓相位不平衡工況下的精確鎖相提供了一種行之有效的理論依據(jù)。所提的不平衡相位檢測和鎖相誤差補(bǔ)償方法，通過對三相電壓采樣值進(jìn)行反正弦運算檢測不平衡相位，并根據(jù)其與鎖相誤差的關(guān)系實現(xiàn)相位補(bǔ)償。該方法結(jié)構(gòu)簡單、易拓展且補(bǔ)償精度高，對相位不平衡下的精確鎖相有著一定的實用價值。

附 錄

為便于表述，這里將式（2）中的1～4表示為

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Phase Estimation Error Detection and Compensation Method of DDSRF-PLL and DSOGI-PLL under Three-Phase Voltage Unbalance

1,21111

（1. School of Electrical Engineering Beijing Jiaotong University Beijing 100044 China 2. State Grid Shanxi Electric Power Company Xinzhou Subsidiary Xinzhou 034000 China）

Due to the combined effect of high-permeability distributed power supply and various types of loads, the three-phase voltage of the actual grid-connected point has deviations in amplitude and phase angle. However, phase-locking methods based on single synchronous reference frame phase-locked loop (SSRF-PLL), such as decoupled double synchronous reference frame phase-locked loop (DDSRF-PLL) and double second-order generalized integrator phase-lock loop (DSOGI-PLL), generally ignored these differences, and, hence, only acquiring synchronization information at phase-balanced three-phase voltage. More is needed to support coordinated control among devices at the grid-connected point. Recently, some methods were presented to obtain phase information of three-phase voltage under phase unbalance, but most suffered from high computation costs and poor expansibility. Therefore, a compensation method for phase estimation error is proposed. The phase estimation error can be accurately compensated under phase-balanced three-phase voltage by detecting the unbalanced phase angle deviation of B and C phases.

Firstly, the three-phase unbalanced voltage specified in the national standard is used as the input signal for DDSRF-PLL and DSOGI-PLL, and the equivalent relationship between unbalanced voltage and phase estimation error of the two phase-locked loops is obtained. The functional relationship between phase estimation error and unbalanced phase angle deviation is based on steady-state characteristics. Secondly, three approximate solutions for the phase estimation errors are given to simplify the calculation. Then, based on the zero-crossing point of the A phase, the unbalanced phase angle deviation of B and C phases is obtained by calculating the sample value of three-phase voltage. Finally, precise compensation of phase estimation error can be achieved by substituting the phase angle deviation in the function of phase estimation error, overlaying the output of phase estimation error to the original PLL reversely. The phase angle deviation detection and phase estimation error compensation method can realize open-loop compensation with a low computation cost and good expandability.

Simulation results under eight conditions of phase angle deviation show that the estimated phase curves of two PLLs always coincide when the unbalanced phase angle deviation of B and C phases change within the range of [-30 ° 30 °]. The maximum error between theoretical and simulation values is 0.230 °, and the relative error is only 2.3 %. It proves the rationality of the theoretical equivalence of two PLLs and the validity of the relationship between unbalanced phase angle deviation and phase estimation error. The results also show that the maximum delay time decreased from 1.126 ms to 28ms, and the corresponding phase estimation error reduced from 20.268 ° to 0.501 °, indicating the method’s high compensation accuracy. The experimental results also have similar conclusions. After the accurate compensation and three approximate methods, the phase estimation error was reduced from 1.425 ms to 75ms, 250ms, 325ms, and 225ms, respectively. The approximate method has a compromise between compensation accuracy and calculation burden.

The following conclusions can be drawn from the simulation and experimental results: (1) DDSRF-PLL and DSOGI-PLL are theoretically equivalent at phase-unbalanced three-phase voltage. (2) The relationship between phase estimation error and phase angle deviation is derived based on the steady-state characteristics of SSRF-PLL, which is suitable for a series of phase-locked methods based on SSRF-PLL and has a wide range of applications. (3) The proposed phase angle deviation detection and phase estimation error compensation method can realize open-loop compensation by simply calculating the sample value of three-phase voltage, which has the characteristics of low computational cost, easy expansion, and high compensation accuracy.

Three-phase voltage unbalance, phase-locked loop (PLL), phase angle deviation detection, phase estimation error compensation

TM46

10.19595/j.cnki.1000-6753.tces.221770

國家自然科學(xué)基金資助項目（52007005）。

2022-09-17

2022-11-11

祁永勝 男，1995年生，碩士研究生，研究方向為電能質(zhì)量治理、并網(wǎng)變換器控制技術(shù)。E-mail: 19121484@bjtu.edu.cn

李 凱 男，1988年生，副教授，碩士生導(dǎo)師，研究方向為電力電子與電力傳動、電氣工程。E-mail: kaili@bjtu.edu.cn（通信作者）

（編輯 陳 誠）