Development of a data acquisition and control system for the International Thermonuclear Experimental Reactor neutron flux monitor

Zihao LIU (劉子豪), Xiang ZHOU (周翔), Renjie ZHU (朱仁杰),Li ZHAO (趙麗), Lingfeng WEI (魏凌峰) and Zejie YIN (陰澤杰)

1 State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei 230026, People's Republic of China

2 Department of Modern Physics,University of Science and Technology of China,Hefei 230026,People's Republic of China

3 Center for Fusion Science of Southwestern Institute of Physics, Chengdu 610041, People's Republic of China

Abstract To satisfy high-precision, wide-range, and real-time neutron flux measurement requirements by the International Thermonuclear Experimental Reactor (ITER), a data acquisition and control system based on fission chamber detectors and fast controller technology,has been developed for neutron flux monitor in ITER Equatorial Port #7. The signal processing units which are based on a field programmable gate array and the PXI Express platform are designed to realize the neutron flux measurement with 1 ms time resolution and a fast response less than 0.2 ms,together with real-time timestamps provided by a timing board. The application of the widerange algorithm allows the system to measure up to 1010 cps with a relative error of less than 5%.Furthermore, the system is managed and controlled by a software based on the Experimental Physics and Industrial Control System, compliant with COntrol, Data Access and Communication architecture.

Keywords: neutron flux monitor, data acquisition, CODAC, EPICS(Some figures may appear in colour only in the online journal)

1. Introduction

The neutron flux monitor(NFM)is one of the most important diagnostic systems applied on many large tokamaks such as the Joint European Torus, Tokamak Fusion Test Reactor [1],and Japan Atomic Energy Research Institute Tokamak-60(JT-60)[2].Analog based systems have been widely used on these machines, however, their instrumentation and control system (I&C) was fairly complicated due to the low integration, which cannot adapt to the contemporary I&C architecture. The International Thermonuclear Experimental Reactor (ITER) is the world's largest magnetic confinement fusion reactor currently under construction, which proposes new challenges for the neutron diagnostic and I&C design.For example, it has a far more lager neutron yield of about 1014-1021n s?1and several NFMs will be deployed to cover the whole dynamic range [3]. For the NFM in ITER Equatorial Port #7 (NFM #7), the maximum measurement range needs to reach nearly 1010cps. The measurement result of each NFM will be used as a parameter to provide the fusion power for real-time feedback control [4], thus requiring fast response and high-precision capabilities with a temporal resolution of 1 ms, a response time less than 1 ms, and a measurement error of less than 10%[5].Furthermore, for the purposes of security assurance, fault analysis, and physics studies, all the raw data acquired from detectors and algorithmic processed data need to be provided along with a precision timestamp, which is known as the ‘no hidden data'principle [6]. For these reasons, it is quite necessary to develop a more powerful data acquisition and control system(DACS) for the ITER NFM.

In recent years, significant progress has been made in high-speed analog-to-digital converter (ADC), field programmable gate array (FPGA) and fast controller technologies, making it possible to solve the above-mentioned issues.Following the principles and methodology described in the Plant Control Design Handbook (PCDH) [6, 7], we have developed a novel NFM DACS making use of these advanced electronic technologies and also the Experimental Physics and Industrial Control System (EPICS) [8] to perform neutron monitoring tasks. Since the 1960s, Campbell's method has been studied and used for high neutron flux measurement and nuclear reactor control [1, 9]. In recent years a wide-range method [10-12] has been developed by the combination of the counting and Campbelling mode. By the application of the wide-range method as well as two fission chambers(FCs)of different sensitivities, the measurement range is expected to reach 1010cps. Furthermore, the large amount of gammarays is of great concern, which may lead to a significant measurement error. So an extra dummy FC is utilized to compensate for the effect of non-neutron background [13].Particularly,the noise tolerance of the system is studied in this work, reflecting a good signal-to-noise ratio margin.

This article is organized as follows. Section 2 introduces the principle and algorithm of the NFM system. In section 3,the system design of NFM DACS is discussed in detail. The experimental performance is presented in section 4, and the conclusion is given in section 5.

2. NFM principle and algorithm

To satisfy the requirements described above, we have been designing a novel NFM system for ITER Equatorial Port#7.The system consists of a detector group, a multi-channel preamplifier, and a corresponding plant control system, as depicted in figure 1.The235U fission chamber is chosen as the neutron detector,which is widely used in harsh environments such as in nuclear reactors, for the advantage of strong gamma suppression capability and wide range of neutron energy response[14].A broader energy response range and a flat response curve are obtained by encasing a polyethylene moderator outside the FCs[14].Each neutron event induces a pulse signal in the FC with only approximately 106electrons.The signal is amplified by a current-sensitive preamplifier with an amplification factor of 0.5 V μA?1, and then transmitted to the acquisition system through a 150 m long cable.The neutron pulses have a width of about 200 ns and an amplitude of about 250 mV. At the low counting rate, the neutron flux can be obtained by counting the pulse individually in each time interval, which is called the counting mode. By setting an appropriate discrimination threshold for the amplitude and width, the counting mode is less sensitive to the background radiation and electronic noise, thus is almost accurate with only statistical uncertainty. At the high counting rate, however, the pulse is indistinguishable due to the pileup and the counting result reaching the upper limit.In this case, the Campbelling mode and current mode are the common methods used to provide high flux measurement[1].

The Campbelling mode, also known as the mean square voltage mode, is applied in this study for its better gamma suppression capabilities, a wider dynamic range, and less influenced by the baseline drift. The principle of the Campbelling mode can be described as

where λ is the average detected neutron rate, Q is the charge of a pulse, and h(t) is the impulse response of the processing circuit. The right side formula of the equation is used as the digitalized Campbelling algorithm.From the simulation study shown in figure 2(a), the Campbelling mode is remarkably affected by background noise at the low counting rate. To provide a consistent measurement covering the whole range,a wide-range algorithm is used by combining the counting mode and Campbelling mode together since the two modes share an overlapping region.This region can be obtained from the simulation result shown in figure 2(b) [11], which is 2 × 104-5 × 105cps when a 5% relative error level is required. The Campbelling result can be dynamically crosscalibrated by the counting result in this region [10], converting its unit to counts per second. This calibration also improves the accuracy of the Campbelling result by eliminating the noise component. A new calibration algorithm based on stratified sampling and the least-squares relative error regression is used in the design to achieve more precise and steady fitting coefficients [15].

The wide-range algorithm can provide a dynamic range of 109cps [16] (counting algorithm covers (1-5) × 105cps and Campbelling algorithm covers 2 × 104-109cps).In order to achieve the required range and provide measurement redundancy,the NFM employs a set of detectors consisting of two235U FCs with different sensitivities and one dummy FC.The sensitivities of the two235U FCs differ by a factor of 10 to extend the system measurement range to 1010cps.The high sensitivity FC is used for the range of 1-109cps and the low sensitivity FC is used for the range of 101-1010cps. The dummy FC is an ion chamber without fissile material which is used for the subtraction of non-neutron background such as gamma-rays and electromagnetic induction.

3. System design

Following the principle and algorithm in section 2 as well as the guidelines published in the PCDH, we developed a data acquisition and control system for NFM #7. As shown in figure 3(a), the system utilizes the fast controller technology based on an industrial PICMG computer (IPC) and the PXI Express (PXIe) platform. It receives the instructions through the Plant Operation Network(PON),publishes plasma control data through the Synchronous Databus Network (SDN), and acquires ITER time through the time communication network[17]. The PXIe chassis is equipped with a high-precision timing device and dedicated signal processing units (SPUs)for the core signal processing task [18]. In addition, the fast controller software based on the COntrol, Data Access and Communication (CODAC) Core System has been developed to manage and control the hardware devices, and also communicate with the CODAC terminals through EPICS.

3.1. SPU

The SPU is specially designed with a fast response, high transmission bandwidth and high input voltage range compatible with 109cps pileup, and commercial products cannot fully meet these requirements. Figure 4 depicts a schematic diagram of the SPU. Firstly, the input signal from the preamplifier needs to pass through the AC-coupling capacitance,which is required by the Campbelling algorithm. This can improve the dynamic range of signal accumulation while removing the preamplifier baseline drift. Secondly, a programmable gain amplifier(PGA),providing 64 levels of gain ranging from-11.5 to 20 dB,is used to adjust the input signal to an appropriate amplitude which is approximately 250 mV.Then, the low-pass anti-aliasing filter limits the signal bandwidth to 10 MHz in order to suppress high-frequency noise before the analog-to-digital conversion. Additionally, a 250 MS s?112 bit pipeline ADC is used for sampling the signal-to-digital waveform data, since the high sampling rate and resolution can improve the discrimination and algorithm accuracy. These large amounts of data are processed by counting algorithm and Campbelling algorithm simultaneously in a high-performance FPGA. By parallel and pipeline processing,both algorithms are executed within each 1 ms interval and their results are immediately available at the end of the time interval, with a very low latency. Additionally, FPGA also implements the PGA control, trigger logic,and bus interface specifications. Three triggering modes are supported, namely software triggering through command,sub-miniature version A (SMA) triggering, and PXI backplane triggering. The PXI bus is used for small data interaction including time-resolved measurement data as well as the control commands while the raw data of the waveform is uploaded through the PXIe bus using the GTX transceivers.Direct memory access (DMA) transmission is utilized to avoid CPU intervention of the IPC, and the on-board DDR3 SDRAM constructs a ring buffer to cache the data between two DMA transmissions.

3.2. Fast controller

In the DACS,one fast controller is employed,which is an IPC connected through a MXI-Express X16 bus to the PXIe-1085 chassis that houses all three SPUs and an NI PXI-6683H. NI PXI-6683H is the selected timing board for synchronization,triggering, and timing. It retrieves the ITER time by connecting to a grandmaster clock through Time Communication Network using the IEEE-1588 Precision Time Protocol,which ensures a time synchronization accuracy of 50 ns RMS and a time-stamping resolution of 10 ns.The PXI-6683H also provides a high-precision and low-jitter 10 MHz clock synchronized to IEEE-1588 as a uniform clock source of the three SPUs, distributing the clock through the PXI clock bus to keep the system in synchronization during long runs.Furthermore, it can generate a signal level at a specific time through one of the backplane trigger lines,so the SPUs can be triggered synchronously.The PXI trigger line is also used for time-stamping. When a measurement result is valid, the SPU would produce a pulse so that PXI-6683H can generate a timestamp for every measurement data.It should be noted that a propagation delay occurring in the cables and preamplifier is intended to be measured and subtracted from the acquired timestamp to improve the time-stamping accuracy in a further work. Through these measures, the fast controller is able to perform real-time measurement with precision timing capabilities,and report the measurement data over the SDN to the plasma control system.

3.3. Software

The system software is developed based on the CODAC Core System, a software infrastructure running on a fast controller as well as other CODAC servers and terminals, which consists of the Red Hat Enterprise Linux system, the EPICS framework,and dedicated tools [19]. As depicted in figure 5,the software can be divided into two parts, the EPICS input/output controller (IOC) and the operator interface (OPI).

The IOC part constructs a distributed database over the PON network and channel access protocol. It adopts a hierarchical design and connects the hardware devices to the record database through a new EPICS layer known as the Nominal Device Support (NDS) [20]. NDS employs asyn-Driver technology [21] and provides a C++ based software framework to manage the EPICS interfaces, proposing a standard method for device integration of generic DAQ and timing devices. Some effort has been put to make SPU compliant with this integration methodology,which results in the SPU kernel driver, SPU library, and ndsSPU driver. The SPU kernel driver is an underlying driver module installed to the Linux kernel, which realizes the register access and data readout of the SPU by means of I/O operation or DMA.And the SPU library is a thin abstraction layer to provide simple application programming interfaces (APIs), mapping every API call to the system call. The ndsSPU driver is the SPU EPICS device module developed based on the NDS templates. It describes the SPU structure and behavior utilizing a set of classes derived from the NDS classes by overriding their class methods. The device functionalities are controlled by process variables (PVs) defined in the EPICS record instance file (.db). NDS is responsible for registering their call-back functions,namely the PV handlers with EPICS.The PV handler is called via asyn-interface during the PV record processing, which in turn, calls the SPU library API for hardware access. Finally, all the EPICS device modules including that for the PXI-6683H are integrated in the NdsIOCApp, which is an EPICS IOC application implemented with the NDS framework.

The OPI part is the human-machine interface(HMI)used for the system operation and supervision. As shown in figure 3(b), the HMI is developed in the Control System Studio, an integrated development and runtime environment conforming to the client Channel Access. This allows the system to be operated from the CODAC terminal by means of PV messages and also allows data access from the IOC database through the PON.

Table 1.The result of the transmission test.

3.4. Operating procedure

The system operating procedure is shown in figure 3(c).Firstly, the system hardware is powered up and services are started for PON and SDN communication.Secondly,the IOC database is configured and initialized, loading drivers to establish a connection of hardware with the database.Thirdly,the system is configured to select a proper operation mode and enable timing board terminals. Before running, the SPU needs to be calibrated, calculating the baseline and amplification introduced by PGA as well as the maximum input noise. The calibration results are applied to set SPU working parameters including the PGA gain and discrimination threshold for counting mode. Then, the IOC launches the DAQ thread, waiting for the trigger and then begins the neutron measurement.Finally,the IOC stops data acquisition when a terminate command is received. It is notable that the system workflow is managed by hierarchical state machines,which are controlled by PV messages. This allows multiscenario and automatic operation using a state notation language program by mapping from the common operating state to the plant system operating state [22].

4. Performance evaluation

Several tests were implemented on the prototype of the NFM DACS to demonstrate its feasibility and evaluate its performance.

4.1. Transmission capability test

For an SPU, the total raw data throughput is 250 M s?1×16 bit = 4 Gbps. Two tests were taken to verify this capability. In the first test, the raw data need to pass through a first in, first out (FIFO) before being uploaded. If the bandwidth cannot support the data rate, the FIFO would be full soon. The data size and the full flag of the FIFO were monitored by an integrated logical analyzer with debug probes through a Joint Test Action Group (JTAG) interface. During the test lasting 2 h, the data residing in the FIFO was always less than half, which provides enough bandwidth to upload the raw data. In order to know the maximum capable transmission rate,another test was done by continuously uploading a data sequence generated by a counter in the FPGA. A simple software was implemented to measure the total transmission time and check the correctness of the data.From the test result shown in table 1, the maximum transmission rate is calculated to be 13.519 Gbps,which is fully capable of uploading the raw data.

4.2. Response time test

In this study, the response time is defined as the time delay from the end of the time interval to the time when measurement results are ready to be published over the SDN, as shown in figure 6(a).It was measured by the following steps.Firstly, the SPU generated a trigger pulse at the end of each time interval, resulting in a precision timestamp (T0) which was acquired through the NI-Sync driver.The algorithm data including the counting and Campbelling values were available immediately afterwards and then acquired by the SPU driver. After that, when the measurement results were obtained and ready to be published,the software acquired the current time (T1) again from PXI-6683H. In this way, the response time of every time interval within 10 s was calculated by T1-T0and is plotted in figure 6(b). This test has obtained an average response time of 0.105 ms and a maximum response time of 0.182 ms.

4.3. HL-2A experiment

Since ITER is still under construction, the system was tested at the HL-2A tokamak with a LB131 fission chamber manufactured by the CNNC-Beijing Nuclear Instrument Factory.HL-2A can provide a neutron source with a neutron yield of 1010n · s-1during 1 MW neutral beam injection (NBI) heating [23]. The neutrons were mainly produced by the fusion reactions between the beam-generated fast deuterium ions and the plasma thermal deuterium ions. Considering that the neutron flux is not very high, only one signal processing channel is used. The maximum noise was measured to be 90 mV before the plasma pulse, so the discrimination threshold was set to 100 mV to remove non-neutron background noise. Figures 7(a) and (b) depict the time-resolved counting and Campbelling measurement results, and figure 7(c) shows the time trace of the NBI power. As the neutral beam was being injected, the measurement results began to rise at 250 ms,and reached the maximum at 272 ms.This is mainly caused by the beam transport and deposition in the fusion reaction region. At 960 ms, the NBI was switched off and the measurement neutron flux also decreased with a decay time of 18 ms due to the classical slowing down and the loss of fast deuterium particles. The fast variation on the counting rate waveform reflects the statistical fluctuation of neutron flux at the detector position,while the slow variation reflects the neutron yield reduction resulting from the beam ion loss during the magnetohydrodynamic activities[24].The counting and Campbelling results reflect great consistency and coincide with the NBI power in terms of time.

4.4. Simulation test

As the experiment in section 4.3 cannot obtain a higher flux,further test focusing on the algorithm performance and noise tolerance of the whole flux range was implemented. A Keysight 81160A arbitrary waveform generator, replacing the detector and preamplifier, was used to generate imitative neutron signals at different counting rates ranging from 103-109cps. A typical generated imitative neutron pulse had a width of 200 ns and an amplitude of 250 mV.Its occurrence time was set to follow a Poisson distribution and the amplitude followed a Gaussian distribution.Moreover,white noise with Vppfrom 50 to 300 mV was superimposed on the imitative neutron signals, respectively. The discrimination threshold was always set to be 10 mV higher than theof the noise. The counting and Campbelling results were compared with the setting counting rate to obtain the measurement error curve, as shown in figure 8(a). The maximum measurement errors of the whole range at different noise levels were picked up and are plotted in figure 8(b).They show that the system has a significant noise suppression capability.The measurement error is always less than 5% if the noise Vppis lower than 250 mV.Note that the Campbelling algorithm also shows good noise tolerance as a result of calibration by the counting value.

5. Conclusion

A novel data acquisition and control system based on the CODAC architecture has been developed and tested for the NFM #7 preliminary design phase. Based on the fast controller technology and the wide-range algorithm implemented in the FPGA,the system is able to perform 1 ms time-resolved neutron flux measurement with a time-stamping resolution of 10 ns, fast response of 0.2 ms, and wide measurement range up to 1010cps. Applications of the PXIe 2.0 interface and DDR3 allow the SPU to upload raw data at a maximum transmission rate of 13.5 Gbps. The system has proven to be of high precision with a relative error of less than 5% in the simulation test. Additionally, a software compliant with CODAC Core System (CCS) was developed to manage and control the system. In the future, a further test with a mini-CODAC provided by the ITER Organization will be performed to verify all the functionalities.

Acknowledgments

This work is supported by National Natural Science Foundation of China (Nos. 11375195 and 11575184) and the National Magnetic Confinement Fusion Energy Development Research (No. 2013GB104003).

ORCID iDs