Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

Sheng-Gang Dong, Xiao-Yang Wang, Hua Fan, Jun-Feng Gao, and Qiang Li

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

Sheng-Gang Dong, Xiao-Yang Wang, Hua Fan, Jun-Feng Gao, and Qiang Li

—This paper makes a review of state-of-thearts designs of successive-approximation register analog-to-digital converters (SAR ADCs). Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert (DAC) and comparator to settle. The 10 bit ADC is simulated in 0.13μm CMOS process technology. The signal-to-noise and distortion ratio (SNDR) is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330μW.

Index Terms—Analog-to-digital converter, asynchronous, clock, review, successive-approximation register analog-to-digital converters.

1. Introduction

Smart phones have become an essential part of everyday life in these few years. With many colorful games and news online, people get close with each other even thousands miles away. Behind these charming applications, the fundamental limit on hardware is still severe, like power, area, and speed. Analog-to-digital converters (ADCs) with moderate speed and resolution are integral in these wireless systems. ADCs that are still under hot research can be divided into four groups in a traditional view. They are the pipeline ADC, sigma-delta ADC, successive-approximation register (SAR) ADC, and flash ADC. The speed and resolution about these four types of ADC are illustrated in Fig. 1[1]. The SAR ADC takes a large part in the moderate speed and resolution section, correlated with the pipeline and sigma-delta ADC. Without the need of power-hungry operational amplifiers, the SAR ADC suits the nanometer semiconductor process advancement and the need for low power better than other structures. Right now, SAR ADCs are the most power-efficient[2],[3]. Its structure is also very simple and only takes small area. However, it has some drawbacks that it is more complicated to realize high-resolution compared with the sigma delta ADC and has much lower speed than flash counterparts. These problems have become tradeoffs in design and directions for improvement.

The SAR ADC roughly works in cycles consisting of two steps: sampling and the sub-cycle of both comparing and the feedback of digital-to-analog convert’s (DAC’s) rearrangement. As shown in Fig. 2, an analog signal is sampled and held before comparison. After the first comparison, the most significant bit (MSB) bit is decided. DAC feeds back the corresponding value, which is taken away from the sampled signal, for the next comparison. Then another comparison begins. The cycles repeat until the least significant bit (LSB) is decided. After that, a new sample phase and MSB decision start. Under this work principle, anN-bit SAR ADC hasNsub-cycles which is clocked at the frequency thatNtimes the sampling clock.

Fig. 1. ADC performance.

Fig. 2. SAR ADC concept.

Fig. 3 reviews papers about SAR ADCs from 2008 to 2013 in ISSCC (IEEE International Solid-State Circuits Conference). It could be seen that the moderate speed (10 MHz to 100 MHz) and resolution (7 bits to 10 bits) section attracts the most attention. Besides that, the section below 10 MHz is also attracting for its ease to realize new ideas about low power and extensive use in biology electronics. The SAR ADCs on the rightmost part take advantage of multiple-channels posing a challenge for flash and pipeline ADCs.

The research about the SAR ADC comes from many perspectives. Often one method has multiple goals. Manually, we separate the researches into three groups by the innovative techniques’ original goal for reviewing convenience. They are low power, high speed, and high resolution. A design falls into one group if it aims to improve one corresponding specification rather than others.

This paper is organized in eight parts. The state-of-the-arts in SAR ADCs for low power are introduced in Section 2. New techniques for high speed and high resolution are reviewed in Sections 3 and 4, respectively. Section 5 illustrates the design procedure for an SAR ADC example and proposes a new clock mechanism. Section 6 introduces the circuit details. Simulation results are given in Section 7. Conclusions are made in Section 8. In Appendix, two tables list the methods mentioned in the text and related papers.

2. Low Power Designs

The SAR ADCs consume the lowest power among all kinds of ADC structures under moderate resolution and speed. Its power mainly is consumed by three parts: the DAC, comparator, and digital controller. For example, the charge-sharing ADC proposed in 2007 draw 0.7 mA from a 1 V supply at 50 M samples per second (Ms/s), the power divided over different blocks as follows: the digital 50%, comparator 35%, and pre-charging 15%[4]. The digital part contains both the DAC and digital controller. Pre-charging is here for illustrating its innovative ideas. According to power makeup, this section is assorted into three blocks to introduce methods used to reduce the power consumption of SAR ADC.

2.1 Feedback DAC

A. Capacitor Array

The capacitor DAC dominates in the SAR ADC design, due to its low mismatch characteristic. The power consumed by this kind of DAC mainly comes from charging and discharging capacitors. Accordingly, improvements are done around this[5]?[8].

Fig. 3. Review of ADC performance in ISSCC.

Traditional SAR ADCs sample the input on the bottom plate of the capacitor array. And the reference voltages on the bottom plate of capacitors are switched between +Vrefand the ground (GND). The split capacitor array method[5]optimizes the switching process to reduce the consumed energy of down conversion to one fifth through dividing the MSB capacitor into two halves to save switching times. This method has a better effect when applied to MSB capacitors, for MSB capacitors are much larger than LSB ones and so is the energy that they need to flip around. But the switch array is a little complicated compared with the next method, top plate sampling[6],[7]. In the top plate sampling technique, the signal is sampled directly at the input of the comparator. The first DAC feedback, which is the most energy-consuming in the traditional method, could be cancelled. And with proper clock generation, the switch array is simple. The merged capacitor switching (MCS)[9]method explores the top plate sampling further. The bias on the bottom plate of the capacitor changes fromVreftoVcmrather than –Vrefor GND. The voltage variation becomes half of the traditional one, which takes advantage of the same concept of charge-redistribution[6]. So is the energy the whole DAC consumes.

A three-bit ADC example is illustrated in Fig. 4 (a)?(c). For every comparison, only half conditions are shown for clearance. The first column is for the sampling phase and the last three is for the comparison phase. For a 10 bit case, the traditional method consumesand the top plate monotonic one consumes. As to the MCS method, it consumes

B. Charge Domain

Except different ways to switch the capacitor bias, the charge domain method is explored as well. Three main methods have been proposed as far as the author knows. In charge domain methods, the reference voltage on one side of some capacitors is biased by charge stored on other capacitors rather than the voltage bias produced inside or outside the chip. Fig. 5 shows the basic idea that the charge from two capacitors merges to produce the requisite reference[3]. The charge is reused to remove the need of the external energy to charge and discharge capacitors. Other two methods[4],[6]are proposed earlier. The first is charge-sharing which utilizes multiple capacitors to store charge, whose number is the same as the resolution of ADC; the second is charge redistribution which breaks the charging process into three sub-ones to save power. Extra cycles are needed in the second method to fulfill the sub-steps.

C. Other Methods

Others methods, like folding, arise from the traditional DACs’ design which have been already illustrated in the classic analog design books[10]. It also saves energy to charge the capacitor DAC and reduce the capacitors’ whole area. For clearance, they will not be illustrated in detail in this paper.

Fig. 5. Concept of charge-reference.

Fig. 6. 65 nm SAR ADC power makeup.

2.2 Comparator

Meta-stability poses a severe limit on the resolution of comparator. It arises from the noise at the input and working robustness of the comparator. To reach a moderate resolution, the comparator has to sacrifice power to suppress the meta-stability conventionally. In recent years, the problem is viewed reversely and utilized to save power.

The dual comparators method[11]was proposed in 2008. When quantizing MSBs, the ADC chooses the high-noise comparator and switch to the low-noise one to decide LSBs. The time to switch is designed by matching the residue resolution with meta-stability of the high-noise comparator. Because the comparator requests less current under the high-noise condition, the ADC saves power to decide MSBs.

The tri-level comparator[12]was proposed in 2011. It designs the meta-stability range of the comparator, which is equal to the LSB’s. Through this, the LSB can be decided through detecting whether the comparator enters meta-stability. In this way, DAC saves half of the capacitor area and the ADC saves a sub-cycle to feed back the DAC output. However, the meta-stability range of the comparator is hard to decide exactly.

2.3 System Level

System level modifications are based on the analysis of the whole ADC operation rather the deliberate optimization for the sub-modules. It is hard to review all methods. Three of them are illustrated.

First, reducing the supply voltage can save power, which is also applied to the SAR ADC. Without the need of operational amplifiers, SAR ADC is especially suitable for the low supply condition[13]. The outstand low power ADC designs all adopt the SAR structures[2],[14],[15]. The low supply which is smaller than 0.6 V, will cause a lot ofproblems such as limited voltage headroom for metal oxide semiconductor field effect transistors (MOSFETs) and more stringent noise specification due to the smaller input range. Even though SAR has a better tradeoff compared with other structures, there are still a lot of problems associated with the low supply voltage[13]?[15].

On the other hand, a lower supply voltage may not lead to lower power, especially at the supply lower than 0.5 V. Because MOSFETs enter the sub-threshold region, without special designs, the system speed is limited, which will increase the leakage current and power consumption[16].

Secondly, except reducing the supply voltage directly, lowering resolution and speed[15]?[17]can also reduce power. Under the low resolution mode, the supply of the ADC is able to scale down proportionally. The power consumed decreases accordingly. Another method is to reduce the circuit area. As shown in Fig. 6[17], 41% of the total power is wasted on the layout parasitic (mainly digital interconnection). So for ideas concerning about saving power, designers have to make tradeoffs with its side effect from the potential of increasing the layout scale.

3. High Resolution Techniques

The resolution of SAR ADCs is usually below 10 bits because of the DAC capacitor matching accuracy. In recent years, researchers pay much attention to digital and analog calibration to overcome this limitation. Besides, new structures combined with comparisons in the time domain and other types of ADCs are proposed. Some of them have very good measurement results. For example, the figure of merit (FoM) of the noise-shaping SAR ADC[18]is 35.8 fJ/conversion, with 62 dB SNDR and 11 MHz bandwidth at 90 MS/s.

3.1 Digital and Analog Calibration

As to the capacitor mismatch, the front-ground digital calibration method[19]was proposed in 1984, which calculates the capacitor mismatch before quantizing and stores the residue error into registers for cancellation in the next step. But it breaks the original working steps of SAR ADC. Background digital calibration is proposed to address this problem. Like the method in the calibration of split-ADC[20], two SAR ADCs are integrated to reduce the capacitor mismatch error through the least mean square algorithm[21],[22]as shown in Fig. 7. The method proposed in [23] also used the least mean square (LMS) algorithm and two sub-ADCs. One sub-ADC is slow but accurate, which is used to calibrate the main ADC. The error is fed into LMS convergence circuits. The digital background technique will not disturb the normal procedure of SAR ADCs, but it is hard to converge and complicated to be integrated on a chip. It usually converges after tens of thousands of testing points.

Fig. 7. Concept of LMS in SAR ADC.

Fig. 8. Sigma-delta concept SAR ADC.

As mentioned in Section 2.2, the input offset voltage of the comparator limits the resolution of SAR ADCs. Often pre-amplifiers are inserted before comparators[24]to reduce the offset and insulate the vulnerable input from the rail-to-rail latch. The SAR ADC[24]adopts a three-stage pre-amplifier, which effectively increases the accuracy of ADC. Another method adopts two comparators and makes use of 1.5 bit redundancy to relax the offset limitation[25]at the expense of extra power. Another way to calibrate the offset of the comparator is adjusting load capacitors to balance differential output currents. However, it is difficult to control the small calibration capacitor incremental step[26].

Error correction is also explored. For simplicity, two of them are illustrated. In the first method, a detector keeps monitoring the output. Once it finds a quantization process wrong, the output of ADC will minus or plus one to LSB according to the error type[11]. The other method realizes the goal through data-driven multiple comparison[2]. Whenever the comparator is found hard to make decisions, it starts a mechanism to repeat the same comparison for five times to make the final decision by using majority voting.

3.2 New Structures

To look for better tradeoffs among power, resolution, and speed, new structures are tried continuously[11],[12],[27]?[32].

The time-domain method is a modification to the comparison process[27]. This method puts the limitation of resolution and speed from the voltage domain to the time domain. It is suited to the smaller and smaller channel length advancement, which can provide a faster switching speed but a lower voltage gain.

The sigma-delta concept was applied in SAR ADCs in recent years[18],[29]. The ADC[29]insertes sigma-delta modulated dithered noise into the input of comparator to suppress the signal-oriented capacitor mismatch. At the output, the already known dithered noise is subtracted fromthe output in digital domain. Another method puts the SAR ADC in a sigma-delta modulated loop and uses the comparator as a 1-bit quantizer[18], as shown in Fig. 8. Thanks to the integrated reference at one input of the comparator, the SAR has a one-order noise shaping effect. The pipeline SAR ADC also provides a better tradeoff. Besides, the ADC[33]splits the high-gain operational amplifier into two to keep the sampling capacitors in two stages far away. In this way, it relaxes the conflict of resolution and speed.

4. High Speed SAR ADC

4.1 Binary-Search

The binary-search SAR ADC accelerates the conversion speed by making the comparison and charge redistribution share the same phase. When the result of the first comparison comes out, one of the 2nd-stage comparators starts the comparison between the input signal and reference level. The result of the first comparison also serves as the control signal to the reference-switching multiplexer in the 3rd stage. Thus the reference voltage settles before the comparison[34].

Through the binary-search, only one of theNcomparators in SAR ADC is activated during each comparison. The power consumption of the comparators is near the same as the conventional one. But different offset voltages of theNcomparators introduce nonlinearity in the ADC, so additional calibration circuits are usually needed.

4.2 Asynchronous

For a conventional synchronous SAR, every clock cycle must tolerate the worst-case comparison time as well as the clock jitter. The asynchronous SAR ADC forms a loop by the comparator, control logic, and DAC. As soon as the current comparison is completed it produces a ready signal to trigger the next comparison[23].

Time of each comparison is not equally distributed. The reduction in the overall comparison time is thus achieved due to the time savings in those faster conversion cycles.

4.3 Multi-Bits Quantizer

Conventional SAR yields one bit per cycle and hence requires at leastNcomparison cycles forN-bit resolution. By converting multi-bit per comparison cycle, the conversion time will be reduced proportionally. The multi-bit per cycle SAR ADC combines the characteristic of flash and SAR[35]. Several DACs and comparators are used to perform the multi-bit per cycle comparison.

The conversion speed of the multi-bit per cycle SAR can be enhanced proportional to the number of bits yielded in each cycle. But the performance of the ADC is vulnerable to the offsets of comparators and mismatch of different arrays.

4.4 Multi-Series-Comparators

The major limitations of the speed for SAR ADCs lie in three aspects: the settling speed of the DAC, yielding time of the comparator, and the digital logic delay. By usingNcomparators in series and connecting the comparator output directly to the reference switch, the multi-series-comparator ADC eliminates the comparators’ reset time and the digital logic delay.

The multi-series-comparator ADC needsNcomparators forN-bit resolution, thus the area of the chip will be larger. Besides, the offsets of different comparators will deteriorate the performance[36],[37].

4.5 Multi-Channels

Usually, two architectures are used for the time interleaved (TI) SAR: hierarchical and pipelined without the T/H hierarchy. For the T/H hierarchy, multiple sub-ADCs are connected to a T/H unit, so the clock and driver signal will be more easily implemented. Compared with the T/H hierarchy, the pipelined without the T/H hierarchy architecture connects multiple sub-ADCs in series to increase the speed of each channel[38]. How to make tradeoffs between power and numbers of channels was discussed extensively in [39] and [40].

A. Calibration

Performance of the TI-ADCs is quite vulnerable to the mismatch of different channels. To overcome the nonlinearity caused by the mismatch, several calibration methods are proposed. One method is to use an additional calibration DAC to measure the gain error and offset of the system at the beginning, then the offset of the comparator is compensated during the normal conversion[41]. Besides the analog feedback method, digital calibration algorithms like LMS are also used.

B. Clock Error Cancellation

Compared to the calibration of offset and gain error, the calibration of timing mismatch is more difficult. References [41]–[43] proposed several calibration methods, but the effect is quite limited for the high speed high resolution ADC. Instead of calibration, the clock generator circuit is often refined to improve the performance[44].

Two tables in Appendix recollect the methods and related papers. As shown above and in the tables, the three aspects of SAR ADCs are balanced with each other. New methods often explore better tradeoffs.

5. Design Example

A design example is presented in this Section. This SAR design is similar to that in [7]. The work flow is shown in Fig. 9. The ADC does not start until the internal sample clock is ready. The internal clock is decided by an array of delay elements. After the frequency of internal clock is adjusted right, the ADC begins comparison and works conventionally. This design facilitates the scalablesampling frequency and provides the potential to reduce power under low sampling speed.

The power, resolution, and speed also need tradeoffs with each other as shown in Fig. 10. For example, the unit capacitor of the feedback DAC is chosen based on this triangle. A large unit capacitor enables low noise operation which is essential for the high resolution ADC, and a small one is beneficial for high speed. Choices are plentiful in the design process. Most of them could be concluded in the tradeoffs triangle (choices triangle).

6. Circuit Details

There are three main parts in this design: the comparator, DAC, and clock generation. DAC is illustrated in Section 2. Comparator is shown in Fig. 11, similar to [7].V+andV?sense the inputs and the internal clock that controls the latch. The inverter before Outpand Outnis an output buffer to drive the next stage. This comparator removes the pre-amplifier so the latch noise and low latching speed may deteriorate the performance of ADC. But with proper choices of unit capacitor and the width of MOSFETs, this problem can be minimized.

The clock generation is shown in Fig. 12. The traditional clock is like Fig. 12 (a)[7]. Clks is the sampling clock and Clk10 is the clock for the 10th comparison. The proposed method is illustrated in Fig. 12 (b). By inserting an array of delay elements, the width of the internal clock can be adjusted and the potential influence of process, voltage and temperature (PVT) on the internal clock can also be balanced out.

7. Simulation Results

The SAR ADC design is simulated in 0.13 μm CMOS process. Power remains below 330 μW when the frequency of the input signal is under 24 MHz. The signal-to-noise and distortion ratio (SNDR) is 54.41 dB, as shown in Fig. 13. The FoM is 15.33 fJ/conv.

Fig. 9. Working flow of the design example.

Table1: Simulation results of design example

Fig. 10. Tradeoffs triangle.

Fig. 11. Comparator.

Fig. 12. Proposed internal clock mechanism.

Fig. 13. Simulation results.

8. Conclusions

In this paper, the state-of-the-arts of SAR ADC designs are reviewed from three aspects: power, resolution, and speed. Different methods are illustrated briefly to achieve an overview as complete as possible. A design example is also proposed to state the design procedure. Besides, a new internal clock mechanism is presented for the potential of reducing ADC power. Under schematic simulation, the 10 bit ADC achieves a 54.41 dB SNDR with 10 MHz input signal and at a sampling rate of 50 MS/s. The FoM is 15.33 fJ/cov.

Appendix

Table 2: Methods review

Table 3: Part of states of the arts design

Acknowledgment

The authors would like to thank Li-Shan Lv and Zhi-Liang Qiao for thoughtful discussions.

[1] A. Matsuzawa, “Essence and technology direction of ADC design,” inProc. ofIEEE Int. Meeting for Future of Electron Devices,Kansai, Suita, 2012, pp. 1–2.

[2] P. Harpe, E. Cantatore, and A. Van Roermund, “A 2.2/2.7 fJ/conversion-step 10/12 b 40 kS/s SAR ADC with data-driven noise reduction,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2013, pp. 270–271.

[3] L. Chang-Yuan, H. Chih-Cheng, C. Liou, and C. Hsieh, “A 2.4-to-5.2 fJ/conversion-step 10 b 0.5-to-4 MS/s SAR ADC with charge-average switching DAC in 90 nm CMOS,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2013, pp. 280–281.

[4] J. Craninckx and G. Van der Plas, “A 65 fJ/conversion-step 0-to-50 MS/s 0-to-0.7 mW 9b charge-sharing SAR ADC in 90 nm digital CMOS,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2007, pp. 574–575.

[5] B. P. Ginsburg and A. P. Chandrakasan, and S. Member,“500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC,”IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 739–747, 2007.

[6] M. Van Elzakker, E. Van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, B. Nauta, M. Van Elzakker, and E. Van Tuijl,“A 1.9 μW 4.4 fJ/conversion-step 10 b 1 MS/s chargeredistribution ADC,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2008, pp. 244–610.

[7] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,”IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731–740, 2010.

[8] Z. Yan, C. H. Chan, U. F. Chio, S.-W. Sin, S.-P. U, R. P. Martins, and F. Maloberti, “A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS,”IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1111–1121, 2010.

[9] V. Hariprasath, J. Guerber, S.-H. Lee, and U.-K. Moon,“Merged capacitor switching based SAR ADC with highest switching energy-efficiency,”Electronics Letters, vol. 46, no. 9, pp. 620–621, 2010.

[10] D. A. Johns and K. W. Martin,Analog Integrated Circuit Design, New York: Wiley, 1997.

[11] V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas, and J. Craninckx, “An 820 μW 9 b 40 MS/s noise-tolerant dynamic-SAR ADC in 90 nm digital CMOS,”inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2008, pp. 238–610.

[12] A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “A 0.5 V 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS,” inProc. of Symposium on VLSI Circuits, Honolulu, 2011, pp. 262–263.

[13] X. Zhou and Q. Li, “A 160 mV 670 nW 8-bit SAR ADC in 0.13 μm CMOS,” inProc. of IEEE Custom Integrated Circuits Conf, San Francisco, 2012, pp. 1–4.

[14] C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, C.-M. Huang, and Y.-T. Shyu, “A 1 V 11 fJ/conversion-step 10 bit 10 MS/s asynchronous SAR ADC in 0.18 μm CMOS,” inProc. of Symposium on VLSI Circuits, Honolulu, 2010, pp. 241–242.

[15] P. Harpe, Y. Zhang, G. Dolmans, K. Philips, and H. De Groot, “A 7-to-10 b 0-to-4 MS/s flexible SAR ADC with 6.5-to-16 fJ/conversion-step,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2012, pp. 472–474.

[16] M. Yip and A. P. Chandrakasan, “A resolutionreconfigurable 5-to-10 b 0.4-to-1 V power scalable SAR ADC,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2011, pp. 190–192.

[17] P. Harpe, C. Zhou, X. Wang, G. Dolmans, and H. de Groot,“A 30 fJ/conversion-step 8 b 0-to-10 MS/s asynchronous SAR ADC in 90 nm CMOS,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2010, pp. 388–389.

[18] J. A. Fredenburg and M. P. Flynn, “A 90 MS/s 11 MHz bandwidth 62 dB SNDR noise-shaping SAR ADC,”IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 2898–2904, 2012.

[19] H. S. Lee, D. Hodges, and P. R. Gray, “A self-calibrating 15 bit CMOS A/D converter,”IEEEJournalofSolid-StateCircuits, vol. 19, no. 6, pp. 813–819, 1984.

[20] J. A. McNeill, S. Goluguri, and A. Nair, “‘Split-ADC’digital background correction of open-loop residue amplifier nonlinearity errors in a 14 b pipeline ADC,” inProc. of IEEE Int. Symposium Circuits and System, New Orleans, 2007, pp. 1237–1240.

[21] J. A. McNeill, K.-Y. Chan, M. C. W. Coln, C. L. David, and C. Brenneman, “All-digital background calibration of a successive approximation ADC using the ‘split ADC’architecture,”IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 58, no. 10, pp. 2355–2365, 2011.

[22] W. Liu, P. Huang, and Y. Chiu, “A 12 b 22.5/45 MS/s 3.0 mW 0.059 mm2CMOS SAR ADC achieving over 90 dB SFDR,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2010, pp. 380–381.

[23] S.-W. M. Chen and R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13 μm CMOS,”IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2669–2680, 2006.

[24] N. Verma and A. P. Chandrakasan, “An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes,”IEEE Journal of Solid-State Circuits, vol. 42, no. 6, pp. 1196–1205, 2007.

[25] M. Furuta, M. Nozawa, and T. Itakura, “A 10-bit, 40-MS/s, 1.21 mW pipelined SAR ADC using single-ended 1.5-bit/cycle conversion technique,”IEEE Journal of Solid-State Circuits, vol. 46, no. 6, pp. 1360–1370, 2011.

[26] G. Van der Plas, S. Decoutere, and S. Donnay, “A 0.16 pJ/Conversion-step 2.5 mW 1.25 GS/s 4 b ADC in a 90 nm digital CMOS process,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2006, pp. 230?231.

[27] A. Agnes, E. Bonizzoni, P. Malcovati, and F. Maloberti, “A 9.4-ENOB 1 V 3.8 μW 100 kS/s SAR ADC with timedomain comparator,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2008, pp. 246–248.

[28] P. Chen, K.-M. Wang, Y.-H. Peng, Y.-S. Wang, and C.-C. Chen, “A time-domain SAR smart temperature sensor with?0.25 to +0.35 Celsius inaccuracy for on-chip monitoring,”inProc. of IEEE European Solid-State Circuits Conf., Edinburgh, 2008, pp. 70–73.

[29] T. Morie, T. Miki, K. Matsukawa, Y. Bando, T. Okumoto, K. Obata, S. Sakiyama, and S. Dosho, “A 71 dB-SNDR 50 MS/s 4.2 mW CMOS SAR ADC by SNR enhancement techniques utilizing noise,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2013, pp. 272–273.

[30] J. Kuppambatti and P. R. Kinget, “A low power zero-crossing pipeline-SAR ADC with on-chip dynamically loaded pre-charged reference,” inProc. of IEEE European Solid-State Circuits Conf., Venice,2013, pp. 113–116.

[31] M. Furuta, M. Nozawa, and T. Itakura, “A 0.06 mm28.9 b ENOB 40 MS/s pipelined SAR ADC in 65 nm CMOS,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2010, pp. 382–383.

[32] B. Verbruggen,M. Iriguchi, and J. Craninckx, “A 1.7 mW 11 b 250 MS/s 2-times interleaved fully dynamic pipelined SAR ADC in 40 nm digital CMOS,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2012, pp. 466–468.

[33] H.-Y. Lee, B. Lee, and U.-K. Moon, “A 31.3 fJ/conversion-step 70.4 dB SNDR 30 MS/s 1.2 V two-step pipelined ADC in 0.13 μm CMOS,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2012, pp. 474–476.

[34] Y.-Z. Lin, S. Chang, Y. Liu, C.-C. Liu, and G.-Y. Huang,“A 5 b 800 MS/s 2 mW asynchronous binary-search ADC in 65 nm CMOS,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2009, pp. 80–81,81a.

[35] Z.-H. Cao, S.-L. Yan, and Y.-C. Li, “A 32 mW 1.25 GS/s 6 b 2 b/Step SAR ADC in 0.13 μm CMOS,”IEEE Journal of Solid-State Circuits, vol. 44, no. 3, pp. 862–873, 2009.

[36] T. Jiang, W. Liu, F.-Y. Zhong, C. Zhong, K. Hu, and P. Y. Chiang, “A single-channel, 1.25-GS/s, 6-bit, 6.08-mW asynchronous successive-approximation ADC with improved feedback delay in 40-nm CMOS,”IEEE Journal of Solid-State Circuits, vol. 47, no. 10, pp. 2444–2453, 2012.

[37] L. Kull, T. Toifl, M. Schmatz, P. A. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, T. M. Andersen, and Y. Leblebici, “A 3.1 mW 8 b 1.2 GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2013, pp. 468–469.

[38] K. Doris, E. Janssen, C. Nani, A. Zanikopoulos, and G. Van der Weide, “A 480 mW 2.6 GS/s 10 b time-interleaved ADC with 48.5 dB SNDR up to Nyquist in 65 nm CMOS,”IEEE Journal of Solid-State Circuits, vol. 46, no. 12, pp. 2821–2833, 2011.

[39] B. P. Ginsburg and A. P. Chandrakasan, “Highly interleaved 5 b 250 MS/s ADC with redundant channels in 65 nm CMOS,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2008, pp. 240–242.

[40] S. M. Louwsma, A. J. M. Van Tuijl, M. Vertregt, and B. Nauta, “A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13 μm CMOS,”IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 778–786, 2008.

[41] W. Liu, Y. Chang, S.-K. Hsien, B. Chen, Y. Lee, W. Chen, T. Yang, G.-K. Ma, and Y. Chiu, “A 600 MS/s 30 mW 0.13 μm CMOS ADC array achieving over 60 dB SFDR with adaptive digital equalization,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2009, pp. 82–83,83a.

[42] A. Haftbaradaran and K. W. Martin, “A sample-time error compensation technique for time-interleaved ADC systems,”inProc. of IEEE Custom Integrated Circuits Conf, San Jose, 2007, pp. 341–344.

[43] S. Huang and B. C. Levy, “Adaptive blind calibration of timing offset and gain mismatch for two-channel time-interleaved ADCs,”IEEE Trans. on Circuits andSystems I: Regular Papers, vol. 53, no. 6, pp. 1278–1288, 2006.

[44] B. Razavi, “Design considerations for interleaved ADCs,”IEEE Journal of Solid-State Circuits, vol. 48, no. 8, pp. 1806–1817, 2013.

[45] C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, C.-M. Huang, C.-H. Huang, L. Bu, and C.-C. Tsai, “A 10 b 100 MS/s 1.13 mW SAR ADC with binary-scaled error compensation,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2010, pp. 386–387.

[46] P. Schvan, J. Bach, C. Fait, P. Flemke, R. Gibbins, Y. Greshishchev, N. Ben-Hamida, D. Pollex, J. Sitch, S.-C. Wang, and J. Wolczanski, “A 24 GS/s 6 b ADC in 90 nm CMOS,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2008, pp. 544–634.

[47] E. Janssen, K. Doris, A. Zanikopoulos, A. Murroni, G. Van der Weide, Y. Lin, L. Alvado, F. Darthenay, and Y. Fregeais,“An 11 b 3.6 GS/s time-interleaved SAR ADC in 65 nm CMOS,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2013, pp. 464–465.

[48] R. Kapusta, J. Shen, S. Decker, H. Li, and E. Ibaragi, “A 14 b 80 MS/s SAR ADC with 73.6 dB SNDR in 65 nm CMOS,”inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2013, pp. 472–473.

[49] Y. M. Greshishchev, J. Aguirre, M. Besson, R. Gibbins, C. Falt, P. Flemke, N. Ben-hamida, D. Pollex, P. Schvan, and S.-C. Wang, “A 40 GS/s 6 b ADC in 65 nm CMOS,” inIEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, 2010, pp. 390–391.

Sheng-Gang Dong was born in Liaoning, China in 1988. He received the B.S. degree in electromagnetic field and radio technology from University of Electronic Science and Technology of China (UESTC), Chengdu in 2011. He is currently pursuing his M.S. degree with the Centre for Communication Circuits and Systems,UESTC.Currently,he is a research assistant with the Centre for Communication Circuits and Systems, UESTC. His research interests include low power analog to digital converters and radio frequency integrated circuits design.

Xiao-Yang Wangwas born in Hubei, China in 1992. He received the B.S. degree in communication and information engineering from UESTC, Chengdu in 2012, where he is currently pursuing the M.S. degree. His research interests include high speed, low power ADCs and other analog and mixedsignal circuits & systems.

Hua Fanwas born in Sichuan, China in 1981. She received the B.S. degree in communications engineering and the M.S. degree in computer science and technology in 2003 and 2006, respectively, both from Southwest Jiaotong University, Chengdu, China. She received the Ph.D. degree from Tsinghua University, Beijing in 2013. She is currently a lecturer with the Department of Communication and Information Engineering, UESTC. Her research interests include low-power and high-speed monolithic A/D converter designs.

Jun-Feng Gao was born in Sichuan, China in 1986. He received the B.S. degree from UESTC, Chengdu in 2009. He is currently pursuing the Ph.D. degree with the Centre for Communication Circuits and Systems, UESTC. Now, he is also working with the Centre for Communication Circuits and Systems, UESTC. His research interests include analog/ mixed-signal integrated circuits design, data converters, and digital signal processing.

Dr. Li was the author of 50+ scientific publications, 2 US/international patents and the bookAnalysis and Design of CMOS Ultra-Wideband Impulse Radio Transceiver(VDP/LAP Lambert Academic Publishing, June 2010). He serves as a member of Editorial Board for theInternational Journal of RF and Microwave Computer-Aided Engineering(SCI-indexed), an AdCom member of the Sichuan Electronics Society of the Chinese Institute of Electronics, and a reviewer for a number of scientific publications and funding agencies. He was the recipient of the 1st UESTC “100-Talent” Program Award (2010), the New Century Excellent Talents Program Award (2011) from the Ministry of Education of China, and a few teaching awards.

eceived the B.Eng. degree in electrical engineering from the Huazhong University of Science and Technology (HUST), Wuhan, China and the Ph.D. in electrical and electronic engineering from the Nanyang Technological University (NTU), Singapore. He has been working on analog/RF and mixed-signal circuits in both academia and industry, holding positions of RTP trainee, senior/research engineer, project leader, and technical consultant during 2001–2009 in Singapore. In 2009 he returned China as a professor at UESTC, Chengdu, where he has brought up the analog group. His research interests include ultra-low voltage and energy-efficient analog/RF and mixed-signal circuits, data converters, and digital-intensive analog design techniques.

Manuscript

November 5, 2013; revised December 2, 2013. This work was supported in part by the National Natural Science Foundation of China under Grant No. 61006027, the New Century Excellent Talents Program of the Ministry of Education of China under Grant No. NCET-10-0297, and the Fundamental Research Funds for Central Universities under Grant No. ZYGX2012J003.

S.-G. Dong, X.-Y. Wang, H. Fan, and J.-F. Gao are with the Centre for Communication Circuits and Systems, University of Electronic Science and Technology of China, Chengdu 610054, China (e-mail: danlucky1988@gmail.com; youngwxuestc@gmail.com; fanhua7531@163. com; fredgaocn@hotmail.com).

Q. Li is with the Centre for Communication Circuits and Systems, University of Electronic Science and Technology of China, Chengdu 610054, China (Corresponding author e-mail: qli@uestc.edu.cn).

Digital Object Identifier: 10.3969/j.issn.1674-862X.2013.04.008